BDD: Figure 49: Total system (source to sink) blocks, ports, & component properties

An expanded version of the spec's Block Definition Diagram (BDD) Figure 49: Total system (source to sink) blocks, ports, & component properties:

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SysPhS-1.1: 'Signal flow is the movement of numbers between system components. These numbers might reflect physical quantities or not. In this example, they do not ... Signals flowing in and out of components are modeled by ports typed by interface blocks that have flow properties typed by numbers.'

SysPhS-1.1: 'In this example, ports are typed by RealSignalOutElement and RealSignalInElement from the signal flow library ... which both have a flow property rSig typed by Real, from SysML, as shown in Figure 49. This value type has no unit, reflecting that the signals are not measurements of physical quantities and do not follow conservation laws.'

SysPhS-1.1: 'The output for SignalSource is named y and is typed by RealSignalOutElement, from the signal flow library ... The input for SignalSink is named u and is typed by RealSignalInElement, also from the library. The signal processor has an input and output, transforming the signal from the source and passing it to the sink.'

Some minor diagramming differences compared with the spec figure version:

- SysML Ports are used (instead of Association ends with composite aggregation and a user-defined «port» keyword).

- The context block TestBed is shown.

- The SignalSource is shown at the top and the SignalSink at the bottom (anticipating the layout in the IBD).

This is a nice expert tool tip:

MagicDraw/Cameo: If you want to show a Property or Port listed both in its corresponding compartment on a Class or Block symbol and as the end of an Association in the same diagram, set the display option Show Association Ends As Attributes/Ports to 'all'

It's done here so one can see the InstanceSpecification source0 of type SignalSource, which is assigned as the defaultValue of inputSignal within the context TestBed, and carries in its Slot for amp the initial value 3.0 for use within the context TestBed (as we'll see next in the IBD).

(On a minor point, the naming of the block property scopeSignalOutput of type SignalSink does not follow Webel Best Practice, because there is nothing in the type name SignalSink that indicates it is a scope. It would be better to have a specialisation of block SignalSink called SignalScope, and then use a consistent name outputSink or such.)

Up next

IBD: Figure 47: Internal structure of test bed from signal source to sink

Notes

[DISPLAY, FEATURE, TOOL]{INFORMATIVE} MagicDraw/Cameo: If you want to show a Property or Port listed both in its corresponding compartment on a Class or Block symbol and as the end of an Association in the same diagram, set the display option Show Association Ends As Attributes/Ports to 'all'

[MODELLING, STYLE]{RECOMMENDED} Webel vs SysPhS-1.1: Recommend use standard SysML Ports instead of block part property with «port» keyword

[ISSUE] Webel vs SysML-1.6: There is no «port» stereotype keyword for Port or Property in UML-2.5.1 or SysML-1.6, it is introduced as a custom (user-defined) stereotype keyword here only to mimic the spec Figure 9-8.

[ANTI-PATTERN, MODELLING] The use of an additional «port» keyword on a Port is usually redundant and causes clutter. The use of an additional «port» keyword on a basic Property is an obsolete trick. Please don't imitate it even if you see it in some specification sample diagrams!

Snippets (quotes/extracts)

[SysPhS-1.1] Figure 49-Figure 50 show block definitions for components of TestBed and SignalProcessor in Figure 47 and Figure 48, respectively.

[SysPhS-1.1] In this example, ports are typed by RealSignalOutElement and RealSignalInElement from the signal flow library ... which both have a flow property rSig typed by Real, from SysML, as shown in Figure 49.

[SysPhS-1.1] The output for SignalSource is named y and is typed by RealSignalOutElement, from the signal flow library ...

[SysPhS-1.1] The input for SignalSink is named u and is typed by RealSignalInElement, also from the library. The signal processor has an input and output, transforming the signal from the source and passing it to the sink.